1. Field of the Invention
The present invention generally relates to CMOS structures and, more particularly, to a method of achieving high performance self-aligned low-resistance raised source/drain for CMOS on SOI, through differential thickness of source/drain and channel, without relying on selective epitaxial growth of silicon.
2. Background Description
Complementary Metal Oxide Semiconductors (CMOS) are electronic components used for Random Access Memory (RAM) and fast data switching. CMOS semiconductors are made of two complementary metal-oxide field effect transistors for high speed and low power use. While many designs have been developed, Silicon On Insulator has recently been of interest due to the high capacity of silicon for high-performance structure fabrication having the channel controllable with low gate voltages.
As silicon film thickness of Silicon On Insulator (SOI)is reduced, for high-performance CMOS fabrication, it becomes necessary to increase the thickness of source/drain regions above the SOI thickness. This principally results from the fact that, as the SOI film becomes thinner, there exists a reduced amount of Si material from which to form silicide for source/drain contacts. Additionally, thinner source/drain regions can degrade on-current due to increased series resistance.
To maintain or reduce the overall source/drain series resistance, including the silicide contact resistance, two methods have been used to form raised source/drain (RSD) structures. First, a method of selective epitaxial growth of silicon has been used that grows the silicon on the source/drain and the top of poly gates, leaving no silicon on gate sidewall spacers.
One key limitation of this method is that epitaxial growth must take place at temperatures as high as 750xc2x0 C., which causes significant transient enhanced diffusion (TED) of major dopants. The unnecessary dopant redistribution in halo/extension regions degrades the performance of devices and short channel immunity. Moreover, with a very thin SOI film, it can be difficult to form epitaxial silicon without causing silicon agglomeration due to possible contamination of carbon in certain chemical vapor deposition tools.
Alternatively, a method of SiGe selective epitaxial growth on source/drain has been used, which provides a sizable Ge fraction. An advantage of this method is that it eliminates the TED of major dopents which may occur at high temperatures.
However, Ge is known to degrade silicide contact formation and contact resistance due to its inherent function as a diffusion barrier. In order to avoid this undesirable result, it is necessary to cap the surface of SiGe with additional epitaxial silicon, using a high temperature process, which may cause TED. High fraction Ge may increase spreading resistance of the RSD layer from the extension to silicide contact. Also, depending on the epi thickness, Ge fraction, and temperature, extended defects such as misfit dislocations can form at the interface between SiGe and Si film of SOI, which may lead to, among other things, junction leakage.
The present invention generally relates to CMOS structures and, more particularly, to a method of achieving self-aligned raised source/drain for CMOS on SOI without relying on selective epitaxial growth of silicon.
In one aspect of the present invention, a method of achieving self-aligned raised source/drain for CMOS on SOI is provided without relying on selective epitaxial growth of silicon.
A principal objective in accordance with a preferred embodiment of the present invention, is to provide a method of building a thicker source/drain without extraneous material formation with epitaxy. In the furtherance of this and other objectives, a method is provided for self-aligned etching of an existing SOI layer to form a channel region thinner than the unetched source/drain regions, instead of thickening the source/drain regions on thinned SOI layer.
A preferred embodiment of the present invention, to increase short-channel immunity for CMOS devices on partially-depleted SOI. In the furtherance of this and other objectives, the channel thickness is modulated as the gate length is reduced. To this end, a CMOS on a SOI is provided with controllable channel thickness to channel length ratios. For example, controlling the increase in channel thickness with shorter channel length.
Further objects, features and advantages of the invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings.